In IC manufacturing processes, metallization processes are used to form metal elements in the IC, such as, for example, busses, interconnects, vias, power distribution networks, etc. In these metal elements, it is necessary for the metal to be reasonably evenly distributed locally in order to ensure that the chemical mechanical polishing (CMP) process, which is used to polish interconnects and dielectric layers in the IC, produces reliable results. To ensure that the metal is evenly distributed locally, IC processes have certain metal density target requirements that must be met. For example, a particular IC process may require the layout to have a metal density in a range of 30% to 70% within a window that is 100 micrometers (microns)-by-100 microns in size as the window is stepped through the entire layout in steps that are 50 microns apart. A tool used during the process checks the metal density within the window as it is stepped through the layout to determine whether the metal density requirements have been met.
As the local metal density requirements become increasingly stringent, the window and step sizes become increasingly smaller. In particular, for IC processes that are capable of achieving nanoscale (e.g., 100 nanometers or less) geometries, the local metal density requirements are so stringent that they may not be met without reducing the conductor widths to an extent that problems associated with IR drop and EM begin to occur. IR drop is a drop in the voltage level being supplied to devices in the IC (e.g., logic gates), which may prevent the IC from operating properly. EM is a transfer of momentum from an electron to a metal ion as the electron passes by the metal ion as the electron moves through a metal conductor. This transfer of momentum can cause the metal ions in the IC to move from their original positions to the extent that physical damage to the conductor occurs, which may result in open circuits and other problems that prevent the IC from operating properly.
FIG. 1 illustrates a top view of a metal conductor runner 2 that has a known metallization pattern designed to meet metal distribution requirements of a particular IC process. The pattern is made up of a layer 3 of metal, such as copper, for example, having rectangular slots 4 formed in it where portions of the metal layer 3 have been removed in order to reduce the local metal density. The pattern is commonly referred to in the IC manufacturing industry as a reverse fill pattern. It is also known in the IC manufacturing industry to use fill, as opposed to reverse fill, patterns that are created by adding, as opposed to removing, metal in order to achieve a target local metal density. A reverse fill pattern is formed during a metallization process that etches away metal atoms to form the slots, which is followed by a CMP process.
In the reverse fill pattern shown in FIG. 1, the rectangular slots 4 are sized and spaced in the metal layer 3 to achieve a target local metal density. The slots 4 are rectangular in shape. Each slot 4 has two opposing lengthwise sides, ls1 and ls2, that are parallel to two opposing lengthwise sides, LS1 and LS2, of the runner 2. Each slot 4 has two opposing widthwise sides, ws1 and ws2, that are parallel to two opposing widthwise sides, WS1 and WS2, of the runner 2. Each slot 4 is separated in the widthwise and lengthwise directions from any adjacent slot 4 by a slot-to-slot spacing distance, S.
The metal runner 2 has a width, W, in the widthwise direction of the runner 2 and a length, L, in the lengthwise direction of the runner 2. The lengthwise and widthwise directions of the runner 2 are perpendicular to one another and to the lengthwise and widthwise directions, respectively, of the slots 4. Electrical current flows through the runner 2 in the lengthwise direction of the runner 2, as indicated by the arrow.
In order to meet stringent metal density requirements and, at the same time, make the runner width W large enough to prevent problems associated with IR drop and EM from occurring, the slot-to-slot spacing distance S is sometimes made very small. Reducing S generally results in a local decrease in the metal density. Eventually, however, this solution will not be adequate due to the fact that S cannot be decreased indefinitely, and metal density requirements are continually becoming increasingly stringent (i.e., window size is continually decreasing). Reducing S results in more area being consumed in the chip by the metal runner because as S is reduced, W generally must be increased in order to ensure that problems associated with IR drop and EM do not worsen.
Another problem associated with the reverse fill pattern shown in FIG. 1 is that it can result in current crowding. Current crowding is a term used to describe a nonhomogeneous distribution of current density in a conductor. Current crowding exacerbates EM and may lead to other problems that affect the performance of the IC, such as localized overheating and the formation of thermal hotspots.
Accordingly, a need exists for a reverse fill pattern that allows increasingly stringent local metal density requirements to be met without exacerbating problems associated with IR drop and EM.